⑴ 誰有CQI-11,12中文版，請傳我郵箱[email protected]
同上，急需 謝謝！！郵箱：[email protected]
⑵ CQI和CSI的區別
CQI是英國專業的協會機構以促進品質管理活動的健康發展，它的前身是於1919年成立的工程檢驗協會。
CQI協會的宗旨是
*提升行業和商業的效率和競爭力。
*促進品質教育和培訓的活動。
*提升品質問題的調查機制。
*維護審計員的培訓課程以及審計員的質量和標准。
CSI是Crime
Scene
Investigation縮寫
意思是：犯罪現場調查
⑶ 求狀態機編寫的數字電子鍾的設計
（先給你個程序，但是這個只有普通的計時功能，定時報數的我現在沒時間加，不知道你是否需要。
這個程序運行時沒問題的，分為頂層、計數3模塊，顯示模塊幾個部分『』『』『）
library ieee;-----------------------這是頂層模塊,
use ieee.std_logic_1164.all;
entity dianzizhong is
port(
clk:in std_logic;
set:in std_logic;
din_s_l:in std_logic_vector(3 downto 0);
din_s_h:in std_logic_vector(3 downto 0);
din_m_l:in std_logic_vector(3 downto 0);
din_m_h:in std_logic_vector(3 downto 0);
din_h_l:in std_logic_vector(3 downto 0);
din_h_h:in std_logic_vector(3 downto 0);
cq_s_l:out std_logic_vector(6 downto 0);
cq_s_h:out std_logic_vector(6 downto 0);
cq_m_l:out std_logic_vector(6 downto 0);
cq_m_h:out std_logic_vector(6 downto 0);
cq_h_l:out std_logic_vector(6 downto 0);
cq_h_h:out std_logic_vector(6 downto 0)
);
end dianzizhong;
architecture art of dianzizhong is
component cnt10
port(clk:in std_logic;
set:in std_logic;
din:in std_logic_vector(3 downto 0);
cq:out std_logic_vector(3 downto 0);
carry_out:out std_logic);
end component cnt10;
component cnt6
port(clk:in std_logic;
set:in std_logic;
din:in std_logic_vector(3 downto 0);
cq:out std_logic_vector(3 downto 0);
carry_out:out std_logic);
end component cnt6;
component cnt24
port(clk:in std_logic;
set:in std_logic;
din_h:in std_logic_vector(3 downto 0);
din_l:in std_logic_vector(3 downto 0);
cq_h:out std_logic_vector(3 downto 0);
cq_l:out std_logic_vector(3 downto 0));
end component cnt24;
component led_driv is
port(din:in std_logic_vector(3 downto 0);
dout:out std_logic_vector(6 downto 0));
end component led_driv;
signal carry1:std_logic;
signal carry2:std_logic;
signal carry3:std_logic;
signal carry4:std_logic;
signal cqi_s_l:std_logic_vector(3 downto 0);
signal cqi_s_h:std_logic_vector(3 downto 0);
signal cqi_m_l:std_logic_vector(3 downto 0);
signal cqi_m_h:std_logic_vector(3 downto 0);
signal cqi_h_l:std_logic_vector(3 downto 0);
signal cqi_h_h:std_logic_vector(3 downto 0);
begin
u0:cnt10 port map(clk=>clk,set=>set,din=>din_s_l,
cq=>cqi_s_l,carry_out=>carry1);
u2:cnt6 port map(clk=>carry1,set=>set,din=>din_s_h,
cq=>cqi_s_h,carry_out=>carry2);
u3:cnt10 port map(clk=>carry2,set=>set,din=>din_m_l,
cq=>cqi_m_l,carry_out=>carry3);
u4:cnt6 port map(clk=>carry3,set=>set,din=>din_m_h,
cq=>cqi_m_h,carry_out=>carry4);
u5:cnt24 port map(clk=>carry4,set=>set,din_h=>din_h_h,
din_l=>din_h_l,cq_h=>cqi_h_h,cq_l=>cqi_h_l);
u6:led_driv port map(din=>cqi_s_l,dout=>cq_s_l);
u7:led_driv port map(din=>cqi_s_h,dout=>cq_s_h);
u8:led_driv port map(din=>cqi_m_l,dout=>cq_m_l);
u9:led_driv port map(din=>cqi_m_h,dout=>cq_m_h);
u10:led_driv port map(din=>cqi_h_l,dout=>cq_h_l);
u11:led_driv port map(din=>cqi_h_h,dout=>cq_h_h);
end art;
----------------------------------------------------------------------------------------
library ieee;-----------------這是cnt6模塊
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt6 is
port(set:in std_logic;
clk:in std_logic;
din:in std_logic_vector(3 downto 0);
cq:out std_logic_vector(3 downto 0);
carry_out:out std_logic);
end cnt6;
architecture art of cnt6 is
signal cqi:std_logic_vector(3 downto 0);
begin
process(clk,set,din)
begin
if set='1' then
cqi<=din;
carry_out<='0';
elsif clk'event and clk='1' then
if cqi="0101" then
cqi<="0000";
carry_out<='1';
else
cqi<=cqi+'1';
carry_out<='0';
end if;
end if;
end process;
cq<=cqi;
end art;
-----------------------------------------------------------------
library ieee;-----------------這是cnt10模塊
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port(set:in std_logic;
clk:in std_logic;
din:in std_logic_vector(3 downto 0);
cq:out std_logic_vector(3 downto 0);
carry_out:out std_logic);
end cnt10;
architecture art of cnt10 is
signal cqi:std_logic_vector(3 downto 0);
begin
process(clk,set,din)
begin
if set='1' then
cqi<=din;
carry_out<='0';
elsif clk'event and clk='1' then
if cqi="1001" then
cqi<="0000";
carry_out<='1';
else
cqi<=cqi+'1';
carry_out<='0';
end if;
end if;
end process;
cq<=cqi;
end art;
-----------------------------------------------------------
library ieee;------------cnt24模塊；
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt24 is
port(set:in std_logic;
clk:in std_logic;
din_h:in std_logic_vector(3 downto 0);
din_l:in std_logic_vector(3 downto 0);
cq_h:out std_logic_vector(3 downto 0);
cq_l:out std_logic_vector(3 downto 0)
);
end cnt24;
architecture art of cnt24 is
signal cqi_h:std_logic_vector(3 downto 0);
signal cqi_l:std_logic_vector(3 downto 0);
begin
process(clk,set,din_h,din_l)
begin
if set='1' then
cqi_h<=din_h;
cqi_l<=din_l;
elsif clk'event and clk='1' then
if (cqi_h="0010" and cqi_l="0011") then
cqi_h<="0000";
cqi_l<="0000";
elsif (cqi_h="0010" and cqi_l="1001") then
cqi_h<=cqi_h+'1';
cqi_l<="0000";
else
cqi_h<=cqi_h;
cqi_l<=cqi_l+'1';
end if;
end if;
end process;
cq_h<=cqi_h;
cq_l<=cqi_l;
end art;
--------------------------------------------------------------------
library ieee;------------------------顯示模塊
use ieee.std_logic_1164.all;
entity led_driv is
port(
din:in std_logic_vector(3 downto 0);
dout:out std_logic_vector(6 downto 0)
);
end led_driv;
architecture art of led_driv is
begin
process(din)
begin
case din is
when "0000"=>dout<="0111111";
when "0001"=>dout<="0000110";
when "0010"=>dout<="1011011";
when "0011"=>dout<="1001111";
when "0100"=>dout<="1100110";
when "0101"=>dout<="1101101";
when "0110"=>dout<="1111101";
when "0111"=>dout<="0000111";
when "1000"=>dout<="0111111";
when "1001"=>dout<="1101111";
when others=>null;
end case;
end process;
end art;
⑷ 什麼是 AIAG CQI-11
汽車行業聯合行小組之表面處理電鍍體系評審
⑸ CQI-9第三版出來了嗎
第三版的較之第二版的增加了將近1/3的內容，刪減了對AMS2750D內容的引用，代之以ALAE CQI-9的具體內容；增加新的過程審核表F-H;