⑴ 谁有CQI-11,12中文版，请传我邮箱[email protected]
同上，急需 谢谢！！邮箱：[email protected]
⑵ CQI和CSI的区别
CQI是英国专业的协会机构以促进品质管理活动的健康发展，它的前身是于1919年成立的工程检验协会。
CQI协会的宗旨是
*提升行业和商业的效率和竞争力。
*促进品质教育和培训的活动。
*提升品质问题的调查机制。
*维护审计员的培训课程以及审计员的质量和标准。
CSI是Crime
Scene
Investigation缩写
意思是：犯罪现场调查
⑶ 求状态机编写的数字电子钟的设计
（先给你个程序，但是这个只有普通的计时功能，定时报数的我现在没时间加，不知道你是否需要。
这个程序运行时没问题的，分为顶层、计数3模块，显示模块几个部分‘’‘’‘）
library ieee;-----------------------这是顶层模块,
use ieee.std_logic_1164.all;
entity dianzizhong is
port(
clk:in std_logic;
set:in std_logic;
din_s_l:in std_logic_vector(3 downto 0);
din_s_h:in std_logic_vector(3 downto 0);
din_m_l:in std_logic_vector(3 downto 0);
din_m_h:in std_logic_vector(3 downto 0);
din_h_l:in std_logic_vector(3 downto 0);
din_h_h:in std_logic_vector(3 downto 0);
cq_s_l:out std_logic_vector(6 downto 0);
cq_s_h:out std_logic_vector(6 downto 0);
cq_m_l:out std_logic_vector(6 downto 0);
cq_m_h:out std_logic_vector(6 downto 0);
cq_h_l:out std_logic_vector(6 downto 0);
cq_h_h:out std_logic_vector(6 downto 0)
);
end dianzizhong;
architecture art of dianzizhong is
component cnt10
port(clk:in std_logic;
set:in std_logic;
din:in std_logic_vector(3 downto 0);
cq:out std_logic_vector(3 downto 0);
carry_out:out std_logic);
end component cnt10;
component cnt6
port(clk:in std_logic;
set:in std_logic;
din:in std_logic_vector(3 downto 0);
cq:out std_logic_vector(3 downto 0);
carry_out:out std_logic);
end component cnt6;
component cnt24
port(clk:in std_logic;
set:in std_logic;
din_h:in std_logic_vector(3 downto 0);
din_l:in std_logic_vector(3 downto 0);
cq_h:out std_logic_vector(3 downto 0);
cq_l:out std_logic_vector(3 downto 0));
end component cnt24;
component led_driv is
port(din:in std_logic_vector(3 downto 0);
dout:out std_logic_vector(6 downto 0));
end component led_driv;
signal carry1:std_logic;
signal carry2:std_logic;
signal carry3:std_logic;
signal carry4:std_logic;
signal cqi_s_l:std_logic_vector(3 downto 0);
signal cqi_s_h:std_logic_vector(3 downto 0);
signal cqi_m_l:std_logic_vector(3 downto 0);
signal cqi_m_h:std_logic_vector(3 downto 0);
signal cqi_h_l:std_logic_vector(3 downto 0);
signal cqi_h_h:std_logic_vector(3 downto 0);
begin
u0:cnt10 port map(clk=>clk,set=>set,din=>din_s_l,
cq=>cqi_s_l,carry_out=>carry1);
u2:cnt6 port map(clk=>carry1,set=>set,din=>din_s_h,
cq=>cqi_s_h,carry_out=>carry2);
u3:cnt10 port map(clk=>carry2,set=>set,din=>din_m_l,
cq=>cqi_m_l,carry_out=>carry3);
u4:cnt6 port map(clk=>carry3,set=>set,din=>din_m_h,
cq=>cqi_m_h,carry_out=>carry4);
u5:cnt24 port map(clk=>carry4,set=>set,din_h=>din_h_h,
din_l=>din_h_l,cq_h=>cqi_h_h,cq_l=>cqi_h_l);
u6:led_driv port map(din=>cqi_s_l,dout=>cq_s_l);
u7:led_driv port map(din=>cqi_s_h,dout=>cq_s_h);
u8:led_driv port map(din=>cqi_m_l,dout=>cq_m_l);
u9:led_driv port map(din=>cqi_m_h,dout=>cq_m_h);
u10:led_driv port map(din=>cqi_h_l,dout=>cq_h_l);
u11:led_driv port map(din=>cqi_h_h,dout=>cq_h_h);
end art;
----------------------------------------------------------------------------------------
library ieee;-----------------这是cnt6模块
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt6 is
port(set:in std_logic;
clk:in std_logic;
din:in std_logic_vector(3 downto 0);
cq:out std_logic_vector(3 downto 0);
carry_out:out std_logic);
end cnt6;
architecture art of cnt6 is
signal cqi:std_logic_vector(3 downto 0);
begin
process(clk,set,din)
begin
if set='1' then
cqi<=din;
carry_out<='0';
elsif clk'event and clk='1' then
if cqi="0101" then
cqi<="0000";
carry_out<='1';
else
cqi<=cqi+'1';
carry_out<='0';
end if;
end if;
end process;
cq<=cqi;
end art;
-----------------------------------------------------------------
library ieee;-----------------这是cnt10模块
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port(set:in std_logic;
clk:in std_logic;
din:in std_logic_vector(3 downto 0);
cq:out std_logic_vector(3 downto 0);
carry_out:out std_logic);
end cnt10;
architecture art of cnt10 is
signal cqi:std_logic_vector(3 downto 0);
begin
process(clk,set,din)
begin
if set='1' then
cqi<=din;
carry_out<='0';
elsif clk'event and clk='1' then
if cqi="1001" then
cqi<="0000";
carry_out<='1';
else
cqi<=cqi+'1';
carry_out<='0';
end if;
end if;
end process;
cq<=cqi;
end art;
-----------------------------------------------------------
library ieee;------------cnt24模块；
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt24 is
port(set:in std_logic;
clk:in std_logic;
din_h:in std_logic_vector(3 downto 0);
din_l:in std_logic_vector(3 downto 0);
cq_h:out std_logic_vector(3 downto 0);
cq_l:out std_logic_vector(3 downto 0)
);
end cnt24;
architecture art of cnt24 is
signal cqi_h:std_logic_vector(3 downto 0);
signal cqi_l:std_logic_vector(3 downto 0);
begin
process(clk,set,din_h,din_l)
begin
if set='1' then
cqi_h<=din_h;
cqi_l<=din_l;
elsif clk'event and clk='1' then
if (cqi_h="0010" and cqi_l="0011") then
cqi_h<="0000";
cqi_l<="0000";
elsif (cqi_h="0010" and cqi_l="1001") then
cqi_h<=cqi_h+'1';
cqi_l<="0000";
else
cqi_h<=cqi_h;
cqi_l<=cqi_l+'1';
end if;
end if;
end process;
cq_h<=cqi_h;
cq_l<=cqi_l;
end art;
--------------------------------------------------------------------
library ieee;------------------------显示模块
use ieee.std_logic_1164.all;
entity led_driv is
port(
din:in std_logic_vector(3 downto 0);
dout:out std_logic_vector(6 downto 0)
);
end led_driv;
architecture art of led_driv is
begin
process(din)
begin
case din is
when "0000"=>dout<="0111111";
when "0001"=>dout<="0000110";
when "0010"=>dout<="1011011";
when "0011"=>dout<="1001111";
when "0100"=>dout<="1100110";
when "0101"=>dout<="1101101";
when "0110"=>dout<="1111101";
when "0111"=>dout<="0000111";
when "1000"=>dout<="0111111";
when "1001"=>dout<="1101111";
when others=>null;
end case;
end process;
end art;
⑷ 什么是 AIAG CQI-11
汽车行业联合行小组之表面处理电镀体系评审
⑸ CQI-9第三版出来了吗
第三版的较之第二版的增加了将近1/3的内容，删减了对AMS2750D内容的引用，代之以ALAE CQI-9的具体内容；增加新的过程审核表F-H;